Corelis – Scan Express Boundary-Scan JTAG testing tools

For more information:

Zvika Almog




What is JTAG Boundary-Scan?

  • The world standard (IEEE-1149.1) method for high speed automatic testing of circuit boards/systems.

  • Detect/isolate circuit board trace opens/shorts, dead/missing devices in seconds, without special fixtures.

  • Program and/or validate non-volatile storage devices in a circuit, for initialization or upgrading.

  • Test functionality at full-speed, via the circuit CPU processor’s diagnostic portal.

  • Field integrity testing/monitoring/upgrading of installed systems.

  • Embedded software development debugging methods (emulation).

  • Accomplish Board Level Hardware Debugging.

    Corelis is the premier provider of JTAG software and hardware tools covering the entire spectrum of these capabilities.

For more information on JTAG technology, please visit Corelis tutorial page on JTAG



Intuitive and High Performance JTAG Boundary Scan Tools

Corelis offers a complete product line of JTAG (boundary-scan) circuit board testing tools called ScanExpress, for interconnect testing and JTAG in-system programming.  Corelis software integrates with a wide selection of JTAG (boundary-scan) hardware controllers, including PCI, PCI Express, USB 2.0, Ethernet/LAN, PXI/cPCI and VXI, with price and performance to meet your specific requirements.

ScanExpress - Tools Family overview brochure



Corelis offers an extensive line of ScanExpress software modules that can be custom tailored to create the right boundary-scan package for any user. Corelis’ ScanExpress software is compatible with Microsoft Windows XP, Windows Vista, and Windows 7 as well as all of Corelis’ hardware platforms.

ScanExpress TPG (Test Pattern Generator)

The ScanExpress TPG™ Intelligent Test Pattern Generator is a state-of-the-art automatic boundary-scan test pattern generation tool that takes the process of boundary-scan automation to a whole new level in performance and ease of use. ScanExpress TPG automatically generates test patterns that facilitate the pin-level fault detection and isolation of all boundary-scan testable nets on a printed circuit board (PCB). ScanExpress TPG also creates test vectors to detect faults on the pins of non scannable components such as clusters and memories that are surrounded by scannable devices. ScanExpress TPG accepts most industry recognized CAE/CAD netlists.

ScanExpress TPG provides an integrated development environment (IDE) in which the user can generate boundary-scan tests from scratch, invoke the ScanExpress DFT Analyzer™ to produce test coverage reports, and invoke ScanExpress Runner™ to execute generated tests, all from a single Graphical User Interface (GUI). The user starts with the basic board design files, adds supplemental information, generates test vectors, creates test coverage reports, and executes the tests by using the descriptive icons located on the shortcuts bar.

By utilizing ScanExpress TPG, both experienced and novice users can create boundary-scan test vectors in a fraction of the time it takes to develop these test vectors using legacy test pattern generators. Test development time is greatly reduced by automating and integrating many of the tasks that the user previously had to perform manually.

ScanExpress TPG greatly reduces the number of keystrokes and mouse clicks and eliminates text editing wherever possible. By maximizing the automation behind the complete process, boundary-scan test procedures can be developed with the least amount of time and effort while ensuring that the final test procedure is of the highest possible quality.

ScanExpress TPG also supports IEEE-1149.6, SerDes devices, BIST (Built-In Self-Test), and hierarchical bridge devices such as the TI 8996 ASP, TI 8997 Scan Path Linker, National SCANPSC110F, National SCANSTA111, National SCANSTA112, Firecron JTS06Bu, and Corelis ScanBridge.  For complete information on ScanExpress TPG, please refer to the detailed datasheet for this product.

ScanExpress TPG (Test Pattern Generator) brochure

ScanExpress DFT Analyzer

Test Coverage Analysis

ScanExpress DFT Analyzer™ is a test coverage calculation tool that provides users with precise pin, net, and device coverage statistics on any board targeted for boundary-scan testing. The tool is able to quantify test coverage into meaningful numbers in which a user can immediately translate to identify areas of a board that are fully tested, partially tested, or are not tested at all. The tool also helps design and test engineers increase fault coverage and reduce boundary-scan test program development time by identifying fault coverage limitations.

ScanExpress DFT Analyzer intelligently combines the testability reports generated by ScanExpress TPG and provides both summary and detailed test coverage reports for the board. Users can view the reports by using the built-in report browser or by importing the data directly to a spreadsheet or database. The combined test coverage reports help engineers to maximize the value of boundary-scan by reducing the need for external test point access to specific nets and pins. The figure to the right depicts a test coverage summary report from the main ScanExpress DFT Analyzer window.

ScanExpress DFT Analyzer is ideally used after schematic capture and before PCB layout. At this stage of product development, ScanExpress DFT Analyzer efficiently creates a set of comprehensive test coverage reports that identify all of the boundary-scan nets and pins, classifying them into basic testability groups. The report also recommends where to add test point pads for physical “bed-of-nails” access if additional test coverage is required using other test methods.

For complete information on ScanExpress DFT Analyzer, please refer to the detailed datasheet for this product.

ScanExpress DFT (Design for Testability Analysis tool) brochure

ScanExpress Runner

Test Program Execution

ScanExpress Runner™ is a run-time boundary-scan execution environment which provides the capability to execute boundary-scan tests and perform In-System Programming in a pre-planned, specific order called a test plan. Test vectors and device programming information generated using ScanExpress TPG, ScanExpress JET, or ScanExpress Flash Generator, are executed and the test results can be displayed on-screen and logged to a file.  Infrastructure, interconnect, resistor and memory tests are executed using a Corelis proprietary Compact Vector Format (CVF) file. This file format maximizes test coverage while minimizing the file size. Other formats such as SVF, JAM, and STAPL are also supported for in-system programming. Any number of different test steps can be combined into a test plan. Test steps within a test plan may be added, removed, reordered, enabled, or disabled. These test steps can be executed sequentially, repeated any number of times, or run continuously. Other features of the ScanExpress Runner test executive include:

  • Pass/Fail test sequence execution and failure reporting

  • Test sequence debugging by forcing selected test steps to skip, stop on failure, or continue

  • Detailed and summary test results and reports to a file

  • Prints test results

  • Allows data entry for operator name, UUT name, model number, serial number, etc.

  • Flow control for changing the flow of test execution dynamically based on previous test results

  • Support for Extensible Test Format (ETF) allowing control of external test equipment such as relay controllers and digital multi-meters

  • Bar code reader support

  • Support for execution from third party test applications and executives

  • Support with any Corelis boundary-scan controller

The main ScanExpress Runner window provides an overview of all test steps and the results of each executed test step. When repeating or looping test steps, these results are displayed both for each individual test as well as for the total test runs executed. When a test step fails, the user has the option to either ignore the result and continue to the next test step or display the vectors in a truth table format to determine the cause of the failure. An optional add-on module called ScanExpress ADO is available with ScanExpress Runner that offers automatic truth table analysis and pin-points failures to the net and pin level. ScanExpress ADO is useful for test operators that have little or no technical background.

For complete information on ScanExpress Runner, please refer to the detailed datasheet for this product.

ScanExpress Runner (Test Execution tool) brochure

ScanExpress ADO

Advanced Diagnostics Option

ScanExpress ADO is an add-on option for the ScanExpress Runner and ScanExpress Runner Gang execution environments. The Advanced Diagnostics Option automates test vector analysis by intelligently deciphering standard truth table diagnostic information and presenting specific fault information to the user in a detailed verbose format. Net and pin level diagnostics information is given for a wide range of tests including infrastructure, interconnect, resistor, and external memories. Other features of the ScanExpress ADO include:

  • Quickly identifies bridging faults, opens and stuck-at conditions

  • Clear fault identification down to the net and pin level

  • Detailed fault report logs

  • Proximity diagnostics

  • Records deterministic and non-deterministic faults

  • Net, pin, and boundary-scan characteristic identification

ScanExpress ADO seamlessly integrates with the ScanExpress Runner test executive requiring no additional learning curve by the user. Once installed, ADO can generate fault reports that are compatible with ScanExpress Viewer to provide superior photographic visual failure analysis.

For complete information on ScanExpress ADO, please refer to the detailed datasheet for this product.

ScanExpress ADO (Advanced Fault Diagnostic tool) brochure

ScanExpress Viewer

Visual Fault Diagnostics

ScanExpress Viewer is a powerful graphical fault identification system that helps to isolate the source and location of faults encountered during boundary-scan testing of printed circuit board (PCB) assemblies. By combining the visual aspects of a photographic image of the PCB assembly with the detailed pad layout information supplied by an industry standard IPC-D-356A netlist, a complete visual representation of the target system is created that facilitates the quick isolation of any failure under investigation.

ScanExpress Viewer allows users with little or no boundary-scan to experience the complete ability to pinpoint the exact source and location of PCB assembly failures. This is true for even the most complex boards and systems with faults that cannot be seen by the naked eye or cannot be detected using x-ray or optical inspection. While the tool is tailored primarily for the manufacturing, testing, and repair processes, ScanExpress Viewer offers a variety of features suited for the design engineer as well such as a parts locator giving the ability to quickly locate small components on a PCB that has no silkscreen or searchable layout drawings.

ScanExpress Viewer requires failure data to be created from ScanExpress Runner using the Advanced Diagnostics Option (ADO). For complete information on ScanExpress Viewer, please refer to the detailed datasheet for this product.

ScanExpress Viewer (Graphical Fault Identification tool) brochure

ScanExpress Merge

System-Level Test

Traditional boundary-scan testing has been primarily used as a complete test and programming solution for single printed circuit board (PCB) assemblies. New technology and software now allow boundary-scan testing to be easily extended to test systems that consist of multiple PCBs, treating them as a single, combined unit.

ScanExpress Merge™ provides users the capability to fully test boundary-scan interconnections across assemblies and modules. This tool can be used to combine multiple target assemblies and treat them as a single boundary-scan compatible target system. ScanExpress Merge has many applications, including:

  • Motherboard and daughter card assembly testing

  • Multiple card chassis testing

  • Gang testing of multiple cards

As motherboard and daughter card assemblies become more commonplace, interconnect testing between these assemblies becomes more critical. The figure to the right depicts a typical multi-assembly system where two daughter boards plug into a main board. Without ScanExpress Merge, interconnect testing for each assembly would be isolated within each module. With ScanExpress Merge, the three assemblies are combined together providing interconnect testability between all three. ScanExpress Merge can be used in a similar manner for any system topology. By preprocessing the test data files of each of the assemblies, ScanExpress Merge generates a unified set of input files that are compatible with Corelis’ ScanExpress TPG Test Pattern Generator. ScanExpress TPG will automatically process the merged assemblies and generate test vectors for the entire combined system, thereby extending boundary-scan testing and programming to the system level. ScanExpress Merge provides an exceptionally easy-to-use setup wizard that contains step-by-step instructions creating a mistake-free environment.

ScanExpress Merge can also automate the process of testing external board I/O and traces that are connected to DIMM memory sockets and connectors. ScanExpress Merge combines the data of the board and the data of the Corelis’ SCANIO parallel I/O modules into a single set of merged input files that are compatible with ScanExpress TPG. Adding support for boundary-scan parallel I/O modules saves time by eliminating the need to describe the connections between the PCB connectors and the modules. To further simplify operations, ScanExpress Merge automatically adds a prefix to the names of items that are associated with each assembly such as net names, reference designators, etc. This allows the user to uniquely identify each assembly within the combined system and to properly diagnose faults when the complete system is tested. The default prefix is optional for each of the merged assemblies and can be specified by the user.

For boards that plug directly into one another via a one-to-one connector, ScanExpress Merge automatically finds and connects the relevant nets on both sides of the connector. The user is only required to specify which connectors are mated. This feature is very useful when using daughter cards that plug into motherboards or cards that plug into a backplane. In addition, ScanExpress Merge automatically generates connection lists for mated connectors and generates suggested wire lists for connections to Corelis SCANIO modules. This allows an engineer to follow ScanExpress Merge’s recommended connection list rather than having to prepare a separate SCANIO-to-UUT connection list manually.

For complete information on ScanExpress Merge, please refer to the detailed datasheet for this product.

ScanExpress Merge (Multi Boards Netlists Merging tool) brochure

ScanExpress Flash Generator

Flash Programming File Generation

When programmable devices such Flash, SEEPROM, CPLD, and FPGA are connected to boundary-scan devices on a circuit board, ScanExpress Flash Generator™ can be used to create programming files to access them via the JTAG interface. The software combines a board netlist, scan-chain information, and BSDL files to automatically generate the necessary scan vectors to perform read, write, erase, and verify operations. ScanExpress Flash Generator boasts a wide range of supported flash devices and manufacturers including Intel, Spansion, Microchip, Samsung, Micron, ST, TI, and many more.

A wide range of features are available with the software including specifying multiple Flash devices for applications involving increased data bus width and address depth, scan-chain optimization and external write strobe access for quicker programming speeds, and a custom device library for adding new devices. The programming files can be executed using either the ScanExpress Programmer™

 or ScanExpress Runner™ execution environments. For complete information on ScanExpress Flash Generator, please refer to the detailed datasheet for this product.

ScanExpress Flash Gen (Flash & other memory devices Programing procedure Generator tool) brochure

ScanExpress Programmer

In-System Programming

The decreasing cost of programmable devices has caused their popularity to explode during recent years. However, the wide variety of available devices and programming methods requires users to acquire and maintain different types of in-system programmers specific to each device manufacturer. As a result, engineers must learn new tools and programming algorithms to program each device causing an inefficient use of engineering resources.

ScanExpress Programmer is designed to replace the clutter of in-system programmers with a single universal programming solution comprised of a scalable architecture for future expandability. ScanExpress Programmer is a universal in-circuit programming tool that can program and verify Flash memories, serial EEPROMs, CPLDs, FPGAs, and other programmable logic devices. ScanExpress Programmer provides common programming functions including read, erase, blank check, program, verify, device ID check, and others. All of these functions can be performed while the target device is installed in-circuit. Users no longer have to maintain different programming tools to program different parts. ScanExpress Programmer offers users one common GUI for all supported programmable devices.

ScanExpress Programmer is targeted for users in development, production, and field environments. For development, software engineers can quickly change code stored in memory devices during the software development process. For production, in-circuit programming allows memory devices to remain on the shelf in a blank state requiring less inventory management. These blank devices can then be installed at assembly and programmed in-circuit, thus reducing programming and tracking costs. In the field, support engineers and technicians can upgrade products with newly released firmware. This provides minimal down-time to customers.

ScanExpress Programmer (Flash & other memory Programming tool) brochure

JTAG Programming

The JTAG programmer module offers the most flexibility and can program Flash memory and serial EEPROM devices which are connected to any boundary-scan component. The JTAG programmer can also program CPLDs and similar devices that are JTAG in-system programmable, including those that are compliant with IEEE-1532.

The illustration below depicts a block diagram of the JTAG programming interface. The JTAG programming module uses a special target Flash description board file and a standard hex or binary data file to program Flash devices. The Flash Programming Information file (.FPI) maintains the JTAG scan chain information and Flash device programming parameters.

The .FPI board files are generated using a ScanExpress Flash Generator license. The ScanExpress Flash Generator user interface is offered as stand-alone generation program, but is more commonly accessed through ScanExpress TPG which has a specialized Flash selection GUI that utilizes a recognized ScanExpress Flash Generator license. Accessing the Flash module from ScanExpress TPG allows users to perform combined JTAG testing along with in-system programming rather than performing these functions separately. The .FPI board files are built using the target netlist, BSDL files, and the built-in Flash library.

I2C and SPI Programming

ScanExpress Programmer provides high-speed programming of I2C and SPI compatible serial EEPROMs and Flash memories. Users can program devices in-system at theoretically maximum programming speeds.

The Inter-Integrated Circuit (I2C) programmer module provides fast programming of I2C memory devices by controlling the I2C bus signals directly through a dedicated I2C interface.

The Serial Peripheral Interface (SPI) programmer module provides fast programming of any SPI memory device by controlling the SPI bus signals directly through a dedicated high-speed SPI interface.

The I2C and SPI interfaces allow erasing, programming, verifying, and reading the content of serial EEPROM and Flash memory devices. Device contents can also be dumped to a file on the computer. Standard Motorola S-Record, Intel Hex, binary, and hex-text file formats are supported. The read button allows immediate display of data from any user specified address block within the serial memory device.

In-System JTAG Programming of CPLDs

In addition to its extensive Flash related features, the JTAG programming module also contains a built-in SVF (Serial Vector Format) file parser which is capable of executing SVF files created by manufacturers’ tools to directly program their CPLDs and FPGAs. The JTAG programming module also contains a JAM and STAPL language interpreter for executing ISP files of the vector-independent JAM and Bytecode formats. Devices from all popular manufacturers are supported including Alliance Semiconductor, Altera, Atmel, Fairchild, Fujitsu, Hyundai, Intel, Microchip, Micron, Macronix, Philips, Samsung, Sharp, SGS-Thompson, Spansion, SST, Texas Instruments, Toshiba, Xicor, and more.

For complete information on ScanExpress Programmer, please refer to the detailed datasheet for this product.


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For more information: Zvika Almog 054-2101400