Sightsys – test program development services for your electronic boards

For more information:

Zvika Almog

zvika@sightsys.co.il

054-2101400

LWDS2-ALL-rear

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Boundary-Scan Test Procedure Development services

Our highly-trained test engineers can produce ready-to-use turn-key boundary-scan test procedures. They process the design information, create all necessary test vectors, verify test vectors on the actual hardware, and provide testability reports.

Sightsys will process your design information, create all necessary test vectors, and verify the test vectors using your actual hardware. This is a complete “turn-key” service resulting in a fully verified and debugged boundary-scan test system. For companies short of resources, those who are under a tight deadline, or for those who are new to boundary-scan and want to be testing in the shortest time possible, this is an excellent way to minimize your investment and maximize your effectiveness.

Some of Sightsys test development services are listed below:

  • Development of a boundary-scan test procedure including test coverage analysis

  • Interconnect, memories, and clusters testing

  • Flash memories and CPLDS programming

  • Parallel testing and programming of thousands of boards

  • ScanReuse application to ensure maximum reuse of test and programming files when moving to Flying probes and ICTs

  • Deploying testing and in-system programming for field service applications

  • Turn key solution including test fixtures

 

Design for Testability Review

Sightsys can provide you with design consultation and an analysis of your design for  boundary-scan testability. We will review your design and make specific recommendations that if implemented will improve the testability. We can also suggest improvements that will increase test coverage and allow boundary-scan to be implemented in a more cost-effective manner.

This service also includes a test coverage analysis that we recommend to do after schematic capture and before PCB layout. At this stage of product development, Sightsys provides you with a comprehensive test coverage reports that identifies all of the boundary-scan nets and pins and classifies them as completely tested, partially tested, or not tested. The report also recommends where to add test points (pads) for physical “nails” access if additional test coverage is required.

 

Test Fixtures & Boundary-Scan/Functional testing integration.

In-Circuit / Gang Programming for mass production.

 Test fixtures offer a versatile way to maximize testability. When designed properly, a test fixture can be reused at multiple test stages, including boundary-scan, ICT and functional. For boundary-scan testing, fixtures offer means to combine multiple boundary-scan chains together, add voltage level shifters, interface to external connectors for increased test coverage, and even test multiple boards simultaneously.

Sightsys can help specify boundary-scan requirements for existing fixtures or can help move the test fixture development process from start to finish by working with our Test Fixture Israeli workshops Partners. Both single unit and multiple unit fixtures are supported to satisfy any level of manufacturing volume.

Sightsys has developed add-on modules for analog signal testing, I/Os connection testing and other modules which can be integrated with the Test Fixture in order to expand test coverage of a given board beyond a standard  boundary-scan technology.

 

On-site Training Classes and Support

Sightsys is able to provide the training class that includes a boundary-scan tutorial and hands-on lab exercises using Corelis ScanExpress hardware and software. Customers also have the option to custom tailor the training class to meet their specific requirements. 

The training includes a combination of lectures, demonstrations, and hands-on exercises using actual hardware to provide you with an overview of ScanExpress test and ISP features and to have you run your own developed test procedures.


What will you be able to do upon completion of the class?

Upon completion of the training you will be able to correctly implement boundary-scan DFT and ISP facilities into your new designs. You will also be able to develop boundary-scan test procedures on your own as well as in-system programming files for CPLDs and Flash memories.

Topics covered in the class include:

  • Introduction to boundary-scan

  • Design for boundary-scan testability Guidelines

  • Design for boundary-scan In-System Programming Strategy

  • Test generation and testing methods for boundary-scan-based designs

    • Test program generation methodology

    • Test program execution plan

    • Test program interactive debugging concepts

  • At-speed embedded functional testing using an on-board JTAG-based CPU

  • In-system programming of CPLDs and Flash memories tutorial

  • Hands-on individual lab exercises using real units under test (UUTs) that will teach you:

    • How to generate and execute interconnect tests

    • How to test memory interconnects

    • How to test logic clusters

    • How to use an embedded processor’s JTAG port for embedded functional testing

    • How to program CPLDs and Flash memories in circuit

    • How to troubleshoot a test procedure

You will become familiar with the entire Corelis ScanExpress product family

 

 

Compilers for C/C++Real Time Operating SystemsDebuggers & JTAG EmulatorsEvaluation Boards & Starter KitsMiddleware & SW componentsHW Testing solutions – Boundary-Scan (JTAG) & FunctionalProtocol and Bus Analyzers & StimulatorsHome of CANopen, EtherCAT, PowerLink, ProfiNet– SW Protocols, devices & SolutionsIn-Circuit/Parallel Engineering & Production Device Programmers (Flash/EPROMs/CPLDs…)Video & Audio SW CODECs components

For more information: Zvika Almog zvika@sightsys.co.il 054-2101400