Networking IP Cores For FPGAs / SoCs

For more information:

Yaron Leizerowitch

yaron@sightsys.co.il

054-2584033

SoC-e – Ethernet communication solutions based on FPGA technology. SoC-e is pioneer in developing a portfolio of IP cores that implement the leading-edge networking and synchronization technologies for critical systems.

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HSR-PRP Switch IP Core

MES – Managed Ethernet Switch IP Core

Unmanaged Ethernet Switch IP Core – Full-crossbar IEEE 1588 Ethernet Switch in a single FPGA 

Profinet Switch IP Core

TSN Switch IP – Time Sensitive Networking Switch IP Core

IEEE 1588-2008 PTPv2

PreciseTimeBasic: IEEE 1588-2008 PTPv2 IP Core

1588 Tiny: IEEE 1588 V2 Slave Only HARD IP Core

IRIGtimeM: IRIG-B Master & Slave IP core

SoC-e has invested a large effort on R&D activity to develop optimized hardware and software architectures to face the challenges that have arisen when implementing these standards. In the same way, SoC-e takes part in most of the interoperability events contributing to the testing and spreading of these new technologies. In order to allow this intensive R&D activity and in internationalization, this company has reinvested all the profits since its creation and it has enforced its strategy with the integration of SoC-e in Etxe-Tar Corporation, an industrial group reference in innovation.

 

HSR-PRP Switch IP Core

HSR-PRP Switch IP Core

 


All hardware low-latency switch for FPGAs

HSR / PRP Switch

HSR-PRP Switch (HPS) is an IP Core for the implementation of High-availability Seamless Redundancy and Parallel Redundancy Protocol (HSR and PRP version 3, IEC 62439-3-Clause 5 and 4 respectively) standards for Reliable Ethernet communications. HSR-PRP Switch is a full hardware solution that can be implemented on a low-cost FPGA.

It is a flexible solution for the Energy Market Equipment that will be connected to HSR rings, PRP Lans or will work as Network bridges in the context of IEC 61850.

HSR/PRP Switch IP Core Brochure

HSR-PRP Switch IP core key features:

  • Fast Ethernet and Gigabit Ethernet supported: 10/100/1000TX -1000FX
  • It supports up to 12 ports
  • It switches frames by hardware. This feature offers high switching speeds, needed to fulfill the Maximum Allowed Age and Data Integrity set for Process Bus and Inter-bay Bus in Electric Substation Automation
  • The processing architecture has been designed specifically for HSR/PRP. Forwarding latencies in range of 500ns for Gigabit Ethernet
  • It is an all-hardware. There is no need for on-chip microprocessor nor software stack
  • It has been optimized to require few logic resources in order to allow the implementation on low-cost FPGA devices
  • It supports IEEE 1588-2008 v2 combined with SoC-e 1588 IP cores
  • It can be used to implement End-Node DAN, RedBox or QuadBox functionalities
  • It has been provided with a single flag that switches between PRP and HSR modes by software
  • It includes complete statistics and error registers for each port integrated (Network Supervision)
  • Supported HSR modes: H, N, T, U,X
  • Supported PRP modes: Duplicates Discard, Duplicates Accept
  • HSR-HSR, HSR-PRP supported modes for seamless PRP-HSR networks merging and Quadbox operation
  • VLAN support and HSR Rings id
  • Evaluation Designs for Spartan-6 and Zynq devices
  • SMNP and MIB Table available
  • Configuration-over-Ethernet (COE): Full access to internal registers through the same Ethernet link that connects to the CPU
  • Dynamic Bitstream Configuration: Allows changing remotely the functionality of the FPGA

HSR-PRP Switch IP core customizable features for optimum resources/functionalities trade off:

  • Node Table size
  • Forwarding Queues size independent for each port
  • IEEE1588v2 P2P Transparent Clock in Redundant and Interlink Ports
  • Scalable duplicate/circulate discard table
  • VLAN Priority support
  • Access to internal registers via MDIO or UART
  • RedBox mode with integrated SAN proxy
  • IEEE 1588v2 Ordinary Clock, Hybrid Clock and Boundary Clock

 HSR_PRP

 

 

 

 

 

 

 

MES – Managed Ethernet Switch IP Core

MES – Managed Ethernet Switch IP Core

DSC_0791SoC-e’s Managed Ethernet Switch (MES) IP core is a non-blocking crossbar matrix that allows continuous transfers between all the ports. It implements a Store & Forward switching approach that fulfills Ethernet standard policy regarding frame integrity checking. The switch buffers and verifies each frame before forwarding it. Nevertheless, the latency time has been minimized to nanoseconds order. Consequently, MES is the perfect switch to implement Ethernet based Industrial Networks.

MES is a tri-speed (10/100/1000 Mpbs) switch IP and supports IEEE 1588 V2 Transparent Clock functionalities. This features modifies PTP event messages taking into account the time spent crossing the switch. This scheme improves distribution accuracy by compensating delivery variability across the network.

Furthermore, MES also supports IEEE 1588 V2 One Step Transparent Clock Peer-to-Peer (P2P) functionality by using independent hardware for each port. This feature allows compensating the residence time but also the delay of each link.

MES can be used in combination with SoC-e HSR-PRP Switch IP to introduce HSR and PRP capabilities in the ports that are required. HSR switching approach is Cut Through. Thus, the combination offers the maximum performance and maximum compatibility with the standards.

MES can be supported on Xilinx Spartan-6 and every 7-Series devices.

Managed Ethernet Switch Brochure

MES IP Core provides MII/GMII/RGMII native interface for Ethernet PHY devices and it can be combined with Xilinx IP to support SGMII among other interfaces.

Managed Ethernet Switch IP Core key features:

  • Full-Duplex Ethernet 10/100/1000base-TX FX interfaces.
  • Configurable 2 to 12 Ethernet ports.
  • MII/GMII/RGMII interfaces for attaching to an external Physical Layer device (PHY).
  • Possible to work with different data rate (10/100/1000base-tx fx Mbps) for each port.
  • Automatic MAC addresses learning and aging (up to 2048 entries).
  • Ethertype Based Switching.
  • Switching Portmask: User-defined forwarding of frames to concrete ports.
  • Port-based VLAN support.
  • MDIO, UART, AXI4-lite or CoE (Configuration-over-ethernet) management interfaces.
  • IEEE 1588v2 Stateless Transparent Clock functionality (P2P – Layer 2/ E2E – Layer 2).
  • IEEE 802.1X EAPOL hardware processing.
  • QoS
    • Priorities (PCP-802.1p, DSCP TOS, Ethertype)
  • RSTP (Software stack required)
    • Hardware support of RSTP.
    • Reference RSTP stack for Linux provided with the IP Core.
    • Posix  Compatible RSTP stack available.
  • MRP (Software stack not required)
    • Ring Manager (MRM)
    • Ring Client (MRC)

MES

- Managed Ethernet Switch IP Core block diagram -

Supported boards for the Reference Designs:

  • Featured boards:
  • Other boards:
    • Xilinx Zynq ZC702 Evaluation Board
    • Fast Ethernet: Xilinx SP605 Evaluation Board and ISM Networking FMC Module
    • Gigabit Ethernet: Xilinx SP605 Evaluation Board and 1000 Base-T Ethernet FMC Card By Inrevium FMC module
    • Avnet Industrial Ethernet Kit

 

 

 

 

 

 

 

 

Unmanaged Ethernet Switch IP Core

Unmanaged Ethernet Switch IP Core

Full-crossbar IEEE 1588 Ethernet Switch in a single FPGA 

DSC_0791SoC-e’s Unmanaged Ethernet Switch IP core (UES) implements a plug-and-play Ethernet switch on reconfi gurable devices. It does not require external confi guration. It has been designed to address the maximum throughput using the minimum resources.

The switch implements a non-blocking crossbar matrix that allows wire-speed communication among all the ports. The switch buff ers and verifi es each frame before forwarding it. Nevertheless, the latency time has been minimized to nanoseconds order. Furthermore, UESsupports IEEE 1588 V2 Transparent Clock functionalities. This feature, that corrects PTP frames introducing the error generated by the switch, allows the interconnection of IEEE 1588 synchronized devices maintaining the highest levels of accuracy.

UES is the perfect Ethernet Switch IP to implement Ethernet based Industrial Networks.

UnmanagedEthernetSwitch IP Core Brochure

UES can be combined with our HSR-PRP Switch IP to introduce HSR and PRP capabilities in the required ports. HSR switching approach is Cut-Through. Thus the combination offers the maximum performance and maximum compatibility with the standards.

Unmanaged Ethernet Switch IP core key features:

  • Plug-and-Play: No con figuration required
  • High Performance: Full-crossbar matrix among ports implemented to allow maximum throughput
  • Fast: Very reduced Latency Times thanks to SoC-e proprietary MAC address matching mechanism
  • Efficient: Optimized to require few logic resources in order to allow the implementation on low-cost FPGA devices
  • Extensible: Zynq version available
  • Flexible: Fully scalable and confi gurable to obtain the best functionalities-size trade-off . The following parameters are available for the designer:
    • Number of ports
    • MAC address table length
    • Buffers queue length
    • IEEE Transparent Clock functionalities
  • Automatic: MAC addresses learning and aging (by default, store capacity of 256 MAC addresses).
  • Media Independent Interface (MII) for attaching to an external Physical Layer device (PHY). 100 Mbps Full-Duplex Ethernet interfaces (Evaluation Design).
  • Gigabit Media Independent Interface (GMII) for attaching to an external Physical Layer device (PHY). 1 Gpbs Full-Duplex Ethernet interfaces.
  • 1588 V2 Transparent Clock functionalities supported (not in the Evaluation Design).

Switch

- UnmanagedEthernet Switch IP Core block diagram -

Supported boards for the Reference Designs:

  • Featured boards:
  • Other boards:
    • Xilinx Zynq ZC702 Evaluation Board
    • Fast Ethernet: Xilinx SP605 Evaluation Board and ISM Networking FMC Module
    • Gigabit Ethernet: Xilinx SP605 Evaluation Board and 1000 Base-T Ethernet FMC Card By Inrevium FMC module
    • Avnet Industrial Ethernet Kit

 

 

 

 

 

 

 

 

Profinet Switch IP Core

Profinet Switch IP Core

shutterstock_30744556_smallThe SoC-e PROFINET Switch IP core is an Intellectual Property (IP) Core for FPGAs. It co-works with a PROFINET software stack running on an external or an internal CPU (Microblaze or ARM9). This IP is an ideal solution for implementing flexible Profinet Automation equipments. The reference design implements PROFINET RT CC-B Line Structure integrating PORT.DE Profinet Software Stack.

PROFINET Brochure

Profinet Switch IP Core key functionalities are:

Port A and Port B: they are connected to a Profinet bus. They connect the equipment to a Line topology network.

Port C: it offers a conventional Ethernet link to any on-board or external CPU in order to receive Profinet frames.

Profinetblock-2

- Profinet Switch IP Basic Structure -

The PROFINET Switch IP Core presents MII interface (10/100 Mbps) towards Interlink Port and towards External Ports connected to Ethernet PHYs. These ports have full-duplex interfaces.

The PROFINET Switch IP Core also presents MDIO interface in order to allow host CPU to access the registers of PROFINET Switch and to poll the status of the connected PHY devices.

The Profinet Switch IP Core includes the following functionalities:

  • This Profinet Switch IP Core supports up to four priority levels. Taking into account that there are eight priority levels in VLAN, these levels are accommodated two by two in the four priority queues that the core can support. This means that priorities zero and one are priority zero – zero being the smallest one – and priorities two and three are priority one, and so on. Nevertheless, the arrangement can be customized.
  • All the ports have four priority queues enabling four different priority levels. In the case of the External Ports, they have another four priority queues related with the forwarding process. Frames forwarded from one External Port to another one have priority over the frames that come from the interlink. Should there be a congestion situation, old frames are dropped from the priority queues.
  • The External Ports PHYs can be accessed from the CPU through a MDIO bus.
  • The Egress port can be selected by tagging the frames sent by the external CPU. There is also an auto-learning MAC table that helps to reduce the network load avoiding unnecessary duplication of frames.
  • The External CPU can write a static MAC table to forward all the frames with a matching destination MAC address to both interlink and the other External destination port.

 

 

 

 

 

 

 

 

 

TSN Switch IP – Time Sensitive Networking Switch IP Core

TSN Switch IP – Time Sensitive Networking Switch IP Core


clocks_rotated_400TSN stands for Time Sensitive Networking. It is the name of the IEEE 802.1 Task Group responsible for standards at Data Link Layer. This group provides the specifications that will allow time-synchronized, low latency, streaming services through IEEE 802 networks.

TSN is unique in that its streams are delivered with guaranteed bandwidth and deterministic latency. There are many features involved in the multiple standards currently under development. Some of the most relevant features and associated standards are:

  • Synchronization: The synchronization is based on IEEE 1588-2008 protocol. A specific profile is defined at IEEE 802.1AS.
  • Preemption: The concept of preemption is supported in TSN. A higher priority frame can interrupt the lower priority frame transmission in order to reduce the latency of time-sensitive streams (IEEE 802.1Qbu & IEEE 802.3br).
  • Traffic shaper: In order to achieve the theoretical lowest possible latency in engineered networks, the Time Aware Shaper functionality is introduced in TSN. This works with applications where time-critical data is sent on regular periodic intervals and it is based on adding time gates on each queue on a port.
  • Redundancy: The high-availability on TSN can be achieved by adding frame replication and elimination as defined in IEEE 802.1CB. In a similar way as defined for HSR, the frames include a sequence number and they are replicated. Each copy is sent through a different path in the network.

TSN is evolving and it is targeting different sectors, like Automotive, Industry, Broadcasting and Aerospace. Therefore, it is expected switching implementations that combine a subset of the available standards and features. This flexibility can be achieved through reconfigurable logic (FPGAs), HDL IPs and embedded software. Thus, programmable SoCs are perfect candidates for TSN implementations.

Time Sensitive Networking (TSN) Switch IP is a non-blocking switching matrix specifically designed to implement Ethernet TSN in Industrial and Aerospace equipment. It can be used as a base for a custom TSN configuration and it can be adapted to support a different subset of the standards.

TSN Switch IP Core provides MII/GMII/RGMII native interface for Ethernet PHY devices and it can be combined with Xilinx IP to support SGMII among other interfaces.

TSN Switch IP Core key features:

  • IEEE 802.AS (IEEE 1588v2 P2P – Layer 2, 802.AS profile).
  • Full-Duplex Ethernet 10/100/1000base-TX FX interfaces.
  • Configurable 2 to 12 Ethernet ports.
  • MII/GMII/RGMII interfaces for attaching to an external Physical Layer device (PHY).
  • Possible to work with different data rate (10/100/1000base-tx fx Mbps) for each port.
  • Automatic MAC addresses learning and aging (up to 2048 entries).
  • Ethertype Based Switching.
  • Switching Portmask: User-defined forwarding of frames to concrete ports.
  • Port-based VLAN support.
  • MDIO, UART, AXI4-lite or CoE (Configuration-over-Ethernet) management interfaces.
  • IEEE 802.1X EAPOL hardware processing.
  • Redundancy: P802.1CB (Standard in draft, technical development in process).
  • Frame preemption: P802.1Qbu (Standard in draft, technical development in process).
  • Schedule traffic: P802.1Qbv (Standard in draft, technical development in process).
  • Traffic policer to limit the excess traffic (the incoming data stream).(Standard in draft, technical development in process).
  • Traffic shaper to limit the transmit rate.(Standard in draft, technical development in process).

Supported boards for the Reference Designs:

 

 

 

 

 

 

 

 

 

IEEE 1588-2008 PTPv2

IEEE 1588-2008 PTPv2

IEEE 1588-2008, also known PTPv2, offers high accuracy clock synchronization for interconnected systems. There are many sectors that benefit from this protocol, like finance, aerospace and industry. A representative IEEE 1588-2008 case-of-use is the adoption of this protocol as synchronization mechanism in the standard for Substation Automation (IEC 61850).

The following diagram shows a typical application of PTPv2 in Substation Automation System (SAS) application:

Diagrama_PTB

 

In this scenario, the Merging Units sample current and voltage values and timestamp them using IEEE 1588 synchronized timers. The protection relays, IEDs, process these values and reconstruct the status of the grid using these digital values. The IEDs attending this information can apply any control action.

An IEEE 1588 infrastructure requires Master Clock equipment to provide clocking reference, Slave Clocks  synchronize with the Master Clocks and Boundary Clocks to communicate different clock domains. Additionally, all networking equipment should be time-aware devices in order to maintain the same level of accuracy in the whole network. In the context of IEEE 1588, the requested featured is named Transparent Clock.

SoC-e provides technology to integrate these functionalities in a very diverse range of equipment:

  • PreciseTimeBasic IP: Ordinary Clock (Master and Slave Clock) and Boundary Clock
  • 1588Tiny IP: CPU-less IEEE 1588 Slave-only clock
  • Managed and Unmanaged Ethernet Switch IP: IEEE 1588 Transparent Clock
  • HSR/PRP Switch IP: IEEE 1588 Transparent Clock with Redundancy Support
  • SMARToem module: 1588-aware networking module for 10/100TX Ethernet (up to six ports)
  • SMARTzynq module: 1588-aware networking module for 10/100/1000TX or 1000FX Ethernet (up to six ports)

 

 

 

 

 

 

 

 

 

PreciseTimeBasic: IEEE 1588-2008 PTPv2 IP Core

PreciseTimeBasic: IEEE 1588-2008 PTPv2 IP Core

shutterstock_93298309PreciseTimeBasic is a IEEE1588-2008 V2 compliant clock synchronization IP core for Xilinx FPGAs. It is capable of accurately time stamp IEEE 1588 telegrams and also to provide a compatible timer. All these processes are carried out by hardware modules.

PreciseTimeBasic IP comprises different hardware and software elements:

  • A hardware Time Stamping Unit (TSU)capable of accurately time stamp IEEE 1588 event messages and to provide an adjustable timer with submicrosecond precision. In fact, two versions of TSU are provided with the PreciseTimeBasic: PTB TSU and PTBLite TSU.
  • PTB TSU has been designed to be connected to the Medium Independent Interface ([G]MII), between MAC and PHY, parsing all the Ethernet frames and inspecting which ones are IEEE 1588.

ptb

  • PTBLite TSU takes advantage of the PTP parser contained in the Zynq GMACs to provide a TSU usingless FPGA resources but with some limitations imposed by the IEEE 1588 hardwired logic on the PS GMAC.

ptbl

Both versions of TSU can use an internal adjustable timer or take its timer value from another TSU. Thus multiple Ethernet connections can share the same timer or different Ethernet connections may have their individual timer.

  • A software PTP Reference Design. SoC-e provides a Linux kernel patch that allow accessing the  TSUs using the Linux PTP Hardware Clock (PHC) subsystem. A modified version of the Open Source LinuxPTP software stack with additional features is also provided. Because of its modular design, porting to other operating is feasible.

PreciseTimeBasic IP Core key features:

Hardware features:

  • Available for Vivado (IP Integrator) and XPS (PCore) tools
  • Supports different Xilinx FPGA Families (Zynq, Spartan6, Artix7).
  • 10/100/1000Mbps Interfaces supported
  • 32 bit seconds / 32 bit nanoseconds counter
  • 32 bit subnanosecond frequency adjust
  • One Pulse Per Second Output available
  • Frequency Selectable Output available (1 KHz/2 KHz/4 KHz/8 KHz/16 KHz/32 KHz)
  • IRIGb Master Output
  • Minimum FPGA resources utilization

Software features:

  • Ordinary Clock and Boundary Clock operation
  • End-to-End and Peer-to-Peer delay mechanisms support
  • Support for PTP on both Layer 2 (Ethernet) and Layer 3 (IPv4) interfaces
  • It can be combined with HSR-PRP and ManagedEthernet IP Cores
  • VLAN support
  • Profiles: Default, Power, Power-Utility, IEEE 802.1AS

The final accuracy obtained in a IEEE 1588 systems depends on many factors (frequency and quality of the local clock, location of the time stamp in the data chain, etc.). As a reference, next figure shows the measured error between the PPS generated by a Commercial Grandmaster equipment and the PPS generated by a Zedboard Avnet Devopment Platfrom which runs LinuxPTP software stack in the ARM processor and uses the PreciseTimeBasic for hardware assisted timestamping (+/- 30 ns).

scope_2

 
 
 
 
 
 
 
 
 
 
 

1588 Tiny: IEEE 1588 V2 Slave Only HARD IP Core

1588 Tiny: IEEE 1588 V2 Slave Only HARD IP Core

PreciseTime basic clocks1588Tiny is a IEEE1588-2008 V2 Slave Only hard-only compliant clock synchronization IP core for Xilinx FPGAs. It is focused on equipments that requires basic IEEE 1588 functionality using the minimum resources. 1588Tiny is capable of accurately time-stamping IEEE 1588 telegrams and also provides a synchronized clock using only hardware modules.

1588 Tiny Brochure

An embedded processor is not required, nor a generic Ethernet MAC. 1588Tiny includes an optimized Ethernet MAC to process PTP frames. It supports Power Profile and IEC 61850 and it can also support other profiles. The reference design targets AVNET Spartan-6 FPGA LX9 Microboard.

1588Tiny key features:

  • IP core netlist ready for seamless integration in ISE design flow
  • Reference design for AVNET Spartan-6 FPGA LX9 Microboard
  • Available profiles: Power, IEC 61850 and Telecom

 

 

 

 

 

 

 

IRIGtimeM: IRIG-B Master IP core

IRIGtimeM: IRIG-B Master IP core

The term IRIG signals is  used to refer to a whole group of serial timecodes, which use a continuous stream of binary data to transmit information on date and time. The individual time code formats can be distinguished by the signal characteristics, e.g. modulated versus unmodulated, which require different ways of signal transmission, by the data rate, and by the kind of information included in the transmitted data.

Back in 1956 the TeleCommunication Working Group (TCWG) of the American Inter Range Instrumentation Group (IRIG) was mandated to standardize different time code formats, resulting inIRIG Document 104-60. The latest revision is IRIG Standard 200-04 which is the current version specifying some new codes which also transmit a year number. IRIGB is widely used to synchronize systems in Substation Automation Systems (SAS) and in Defence and Aerospace. Nowadays, it is quite frequent combining IEEE 1588 systems with IRGIB systems. The following diagram maps as an example the functionalities of SoC-e timing related IPs of SAS equipment related to synchronization.

Diagrama_IRIGB_PTB_irigM

 
IRIGtimeM implements an IRIG 200-04 compliant time synchronization master on FPGA devices. This IRIG-B master IP has been designed to support all the IRIG-B coded expressions as well as DCLS and AM modulations in order to provide maximum flexibility.
 

 

 
 

 

This IRIG-B master IP generates IRIG-B frames each second, including the mandatory and optional time information (seconds, minutes, hours, days, years, control functions and binary straight seconds) depending on the IRIG-B time code selected on the confi guration. This IP has been designed to provide autonomous operation, requiring as less con figuration as possible. The standard features included in IRIGtimeM IP core are:

 

  •  IRIG 200-04 compliant time synchronization master
  •  Support for DCLS and AM modulations
  •  Support for all IRIG-B coded expressions, including year information, control functions and
    straight binary seconds
  • Output type (IRIG-B timecode) con figurable both before implementation and on
    the fly
  • Precise IRIG-B output in order to provide nanoseconds precision
  • 32-bit timestamp input for initial set up of the IP
  • Periodic pulse output for testing
IRIGtimeM IP core block diagram is represented in the following figure:
 
 
irigtime_m_main
 
 
 
 
IRIGtimeM IP core block is supported in several Xilinx FPGA families. As a reference, these are the resources needed on the smaller Spartan-6 fpga (LX9)
 
  • 625 Slices
  • 868 Slice Registers
  • 1840 LUTs
  • 7 RAMB16BWER memory block
  • 4 DSP48A block
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For more information: Yaron Leizerowitch yaron@sightsys.co.il 054-2584033